Generating the geometry is the easy part. What bites is verification: DRC and ERC catch geometry and miss intent, and a board can pass both while still being wired wrong because the schematic said so. For anything headed to copper I'd want the agent to hand back the netlist and a diff rather than a render. Same for assemblies, where interference and tolerance checks decide whether a plausible model becomes a real part. Ordering is the moment review stops being optional, and that is where the human gate belongs.