Alba 🌸 :v_pat: on nostr

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Alba 🌸 :v_pat: · 1w

I'm not sure how best to solve this. maybe I could insert a global buffer instance to force a specific network to be used for the clock, that should tie the timing enough i guess

Alba 🌸 :v_pat: @Alba 🌸 :v_pat: 1784378722

do any of you know how to programmatically query nextpnr for things like delays from a bel pin to another? that'd be wonderful here

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Alba 🌸 :v_pat: · 1w

anyway, i have finished patching hackrf_transfer, libhackrf and the firmware to remove buffering and I've made a simple python script that should replay a .pcap. all is ready to test the transmitter there's no way it will work though

Alba 🌸 :v_pat: · 1w

IT WORKED :neofox: the FPGA pipeline was flawless, but i had a mistake in my python script that took a bit to find I have a more or less complete PHY :neofox_heart: