Damus

Recent Notes

Alba ๐ŸŒธ :v_pat: · 1w
okay so now the bulk of the work moves to the MCU... i need to implement the MAC. will I? who knows..
Alba ๐ŸŒธ :v_pat: · 1w
IT WORKED :neofox: the FPGA pipeline was flawless, but i had a mistake in my python script that took a bit to find I have a more or less complete PHY :neofox_heart:
Alba ๐ŸŒธ :v_pat: · 1w
anyway, i have finished patching hackrf_transfer, libhackrf and the firmware to remove buffering and I've made a simple python script that should replay a .pcap. all is ready to test the transmitter there's no way it will work though
Alba ๐ŸŒธ :v_pat: · 1w
IT WORKED :neofox: the FPGA pipeline was flawless, but i had a mistake in my python script that took a bit to find I have a more or less complete PHY :neofox_heart:
Alba ๐ŸŒธ :v_pat: · 1w
do any of you know how to programmatically query nextpnr for things like delays from a bel pin to another? that'd be wonderful here
Alba ๐ŸŒธ :v_pat: · 1w
seems like it's none of the above. instead it was a clock timing problem; i was sampling the ADC inputs at the wrong time. my current best explanation for what's happening: the FPGA gets the ADC cloc...
Alba ๐ŸŒธ :v_pat: profile picture
I am so happy. you cannot imagine. this thing has been blocking me for weeks :neofox_melt_3:

I actually got that suspicion a week ago but hadn't had time to verify it until today. I inserted an extra LUT and everything works, so I think I'm correct...
1
Alba ๐ŸŒธ :v_pat: · 1w
I'm not sure how best to solve this. maybe I could insert a global buffer instance to force a specific network to be used for the clock, that should tie the timing enough i guess
note1th2w7...
Alba ๐ŸŒธ :v_pat: profile picture
seems like it's none of the above. instead it was a clock timing problem; i was sampling the ADC inputs at the wrong time.

my current best explanation for what's happening: the FPGA gets the ADC clock, but it needs to sample 8ns after the edge to get good data. so what they currently do is inserting a single LUT to provide that delay. it looks like as I added stuff to my design, the PnR decided to use a different global network to host the delayed clock signal. the new global buffer is much closer to the LUT than the previous one, so the delay is reduced and I was sampling garbage
1
Alba ๐ŸŒธ :v_pat: · 1w
I am so happy. you cannot imagine. this thing has been blocking me for weeks :neofox_melt_3: I actually got that suspicion a week ago but hadn't had time to verify it until today. I inserted an extra LUT and everything works, so I think I'm correct...