seems like it's none of the above. instead it was a clock timing problem; i was sampling the ADC inputs at the wrong time.

my current best explanation for what's happening: the FPGA gets the ADC clock, but it needs to sample 8ns after the edge to get good data. so what they currently do is inserting a single LUT to provide that delay. it looks like as I added stuff to my design, the PnR decided to use a different global network to host the delayed clock signal. the new global buffer is much closer to the LUT than the previous one, so the delay is reduced and I was sampling garbage