seems like it's none of the above. instead it was a clock timing problem; i was sampling the ADC inputs at the wrong time.
my current best explanation for what's happening: the FPGA gets the ADC cloc...
I am so happy. you cannot imagine. this thing has been blocking me for weeks :neofox_melt_3:
I actually got that suspicion a week ago but hadn't had time to verify it until today. I inserted an extra LUT and everything works, so I think I'm correct...
I actually got that suspicion a week ago but hadn't had time to verify it until today. I inserted an extra LUT and everything works, so I think I'm correct...
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